High precision, large bit digital to analog converters (“DACs”) often use segmented resistor architectures, “R-2R” architectures, or hybrid architectures. In each architecture, the DAC is populated by an array of switch-controlled resistor segments that are individually switched to a high reference voltage (“VHI”) or to a low reference voltage (“VLO”) in response to a digital input code. When such DACs are manufactured in integrated circuits, mismatch among the different resistors can lead to non-linear behavior and, therefore, loss of precision.
Previous attempts to address these issues have primarily focused on trimming or similar methods. Laser trimming allows for the adjustment of the resistors to more ideal values with a much lower tolerance. This method however, is largely impractical, inefficient, and costly to perform on a continuing basis. Other attempts have addressed the modification of the R-2R ladder by removing and scaling resistors in paths corresponding to the least significant bits (“LSBs”). Such methods however, require the use of long resistor units, and thus the amount of time it takes the signal to reach the output differs among the paths, resulting in glitches at the output.
There is a need in the art for a high precision, large bit DAC architecture that retains precision even in the presence of resistor mismatch. The present disclosure is directed to such needs.